A Possible 100 MSPS Altera FPGA FFT Processor

This document describes a FPGA implementation and simulation of the FFT component of the IIP Radiometer RFI processor described in [1]. The FFT processor will ideally be capable of processing 100% of the input bandwidth (100 MSPS.) The chosen FFT length (1024) is a trade off of FFT bin width (approximately 100kHz) and possible RFI detection. This document describes a possible implementation in an Altera FPGA, as opposed to currently available ASIC designs [2, 3]. These ASICs are capable of performing FFTs on 100 and 84 MSPS data streams continuously using two ASICS chained together (16W of power.) They come in large Ball Grid Array packages which may propose difficulties in assembly. There are many other FFT processors available [4], however most are significantly slower, or are sold as modules. Investigations are continuing in this area. This document is broken into three separate sections. The first section describes the Altera FFT Megacore. Secondly, simulation results are presented from the core. Finally, several ideas are proposed for a 100 MSPS FFT processor.